Integrated circuit devices are universally present in essentially every type of electronic system. The various mechanisms by which an integrated circuit device can fail have been the subject of extensive research and literature. One of the primary quality concerns of integrated circuit manufacturers is that devices which are functional when shipped to the customer will fail at some distant time in the future from one or more of a variety of failure mechanisms that are difficult or impossible to detect during the infant stages of the device's lifetime. Integrated circuit manufacturers typically attempt to insure the long term reliability of integrated circuit device by subjecting the device to a set of conditions typically involving elevated temperatures, elevated operating voltages, or both. These conditions are designed to accelerate the onset of any failure mechanisms that the device may exhibit. One well known type of reliability testing is frequently referred to as burn-in. During a typical burn-in sequence, a predetermined set of voltages are applied to specific inputs of the integrated circuit and maintained for an extended period of time. Typical burn-in sequences may be maintained for a duration of anywhere from 24 to 2,000 hours or more. Those familiar with semiconductor fabrication in general and with semiconductor testing in particular will appreciate that the duration required to adequately burn-in a device is extremely long and, thus, it is desirable to be able to burn-in multiple devices simultaneously to minimize the cost of the burn-in test.
Historically, burn-in testing did not occur until after the integrated circuit device had been packaged. After packaging, an integrated circuit device was typically inserted into a socket attached to a relatively large printed circuit board capable of simultaneously burning in a large number of devices. To avoid the cost associated with packaging devices that would ultimately fail at burn-in and to accommodate burn-in of direct chip attach (DCA) applications such as "flip chip" devices in which the device is not packaged in a traditional package at all, integrated circuit manufacturers have devised methods for burning in integrated circuits at the wafer level. In Dasse, et al., U.S. Pat. No. 5,399,505 and Dasse, et al U.S. Pat. No. 5,654,588 (both of which are both incorporated by reference herein), an apparatus and method for performing wafer level burn-in are disclosed. Wafer level burn-in is the process of simultaneously burning in all of the devices on an entire wafer prior to final assembly or packaging of the devices.
In a typical wafer level burn-in application, multiple devices are connected in parallel to a common power supply or signal generator. The multiple devices connected to any single power supply or signal generator define a cluster or group. If one or more of the devices in a cluster is defective such that it draws an excessively large current when the burn-in test conditions are applied, the excessive current draw will prevent the power supply from providing the necessary voltages to the remaining devices in the cluster. When this situation occurs, the remaining devices in the cluster are prevented from being properly burned in. Without receiving proper burn-in, the remaining devices in the cluster typically must be discarded even if they are otherwise functional because the reliability of these devices has not been adequately determined. Thus, in a conventional wafer level burn-in application, fully functional and operational devices often must be discarded because conventional wafer level burn-in testing systems are incapable of isolating defective and high current devices from the remaining devices in the cluster such that the remaining devices receive a proper burn-in signal. While this problem could be addressed by dedicating separate drivers and power supplies to each device on the wafer, the cost of doing so would be astronomical. The fear of discarding large numbers of functional devices because of a single bad device in a cluster motivates manufacturers to burn-in devices using small clusters, but small clusters result in extra testing cost in the form of additional probing hardware required to probe each cluster and additional power supplies and logic signal generators for each cluster. Therefore, it is highly desirable to provide a solution enabling the wafer level burn-in testing of multiple integrated circuits that is capable of isolating non-functional or defective devices from the burn-in signals during the burn-in test such that the remaining devices receive an adequate burn-in test. It is further desirable that the implemented solution does not significantly increase the hardware required to perform the wafer level burn-in and does not otherwise significantly increase the cost or time required to complete the burn-in.